This disclosure relates generally to the field of semiconductor-on-insulator substrates, and semiconductor structures within and upon semiconductor-on-insulator substrates.
Semiconductor structures include semiconductor substrates on which semiconductor devices, such as but not limited to resistors, transistors, diodes and capacitors, are formed. The semiconductor devices are connected by patterned conductor layers that are separated by dielectric regions.
Within the context of semiconductor substrates that are used in the fabrication of semiconductor structures, semiconductor-on-insulator substrates, such as silicon-on-insulator (SOI), may be used. Semiconductor-on-insulator substrates include a base semiconductor substrate (or handle wafer), a buried dielectric layer (which may be buried oxide, referred to as BOX) located on the base semiconductor substrate, and a relatively thin surface semiconductor layer (also referred to a top silicon layer) located on the buried dielectric layer. Under circumstances where the base semiconductor substrate and the surface semiconductor layer of a semiconductor-on-insulator substrate comprise a single semiconductor material (such as silicon) having a single crystallographic orientation, the semiconductor-on-insulator substrate may under certain circumstances be fabricated by incorporation of a buried dielectric layer within a thickness of a bulk semiconductor substrate.
Semiconductor-on-insulator substrates find many uses in semiconductor structure fabrication, including complementary metal oxide semiconductor (CMOS) structures. However, use of semiconductor-on-insulator substrates for high voltage CMOS devices may result in reduced performance of the high voltage devices. In high voltage semiconductor-on-insulator technology, the handle wafer is grounded during operation, and the top silicon layer above the BOX may be at high potential. In areas of the top silicon layer that are p-type, an accumulation layer may form during operation, while in areas of the top silicon layer that are n-type, an inversion layer may form. These accumulation and inversion layers cause the breakdown performance of the device to be degraded.